Thursday 28th of March 2024
 

5T SRAM Cell with Improved Read/Write-ability and Reduced Standby Leakage Current


Chien-Cheng Yu and Ming-Chuen Shiau

In this paper, a new single-port five-transistor (5T) Static Random Access Memory (SRAM) cell and associated read/write assist circuitries is proposed. Amongst them, a voltage level conversion circuit is to provide a voltage of the respective connected word line to be lower than or equal to a power supply voltage VDD such that the read/write-ability of the cell can be improved. Furthermore, a voltage control circuit is coupled to the sources corresponding to the driver transistors of each row memory cells. This configuration is aimed to control the source voltages of driver transistors under different operating modes. In addition, introducing a two-stage reading mechanism to increase the reading speed and thus to avoid unnecessary power consumption. Finally, with the standby start-up circuit design, the cell can rapidly switch to the standby mode, and thereby reduce leakage current in standby.

Keywords: Static random access memory, Read/write assist circuitry, Voltage level conversion circuit, Voltage control circuit, Standby start-up circuit

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ABOUT THE AUTHORS

Chien-Cheng Yu
Chien-Cheng Yu received the B.S. and M.S. degrees from Feng Chia University and National Taiwan Normal University, respectively. He is currently an Assistant Professor with the Department of Electronic Engineering at Hsiuping University of Science and Technology, Taiwan. His current research interests include design and analysis of high-speed, low-power integrated circuits and low-voltage low-power embedded SRAM circuit design.

Ming-Chuen Shiau
Ming-Chuen Shiau received the B.S., M.S. and Ph.D. degrees in Electronic Engineering from National Chiao Tung University, Hsinchu, Taiwan. He is currently a Full Professor with the Department of Electrical Engineering at Hsiuping University of Science and Technology, Taiwan. His current research interests include low-power digital circuit design, SRAM design and low-voltage embedded memory circuit design.


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