Designing A Re-Configurable Fractional Fourier Transform Architecture Using Systolic Array
FRFT (Fractional Fourier Transforms) algorithm, which has been derived from DFT, computes the angular domains within the time and frequency domains. This algorithm is increasingly used in the field of signal filtering, quantum mechanics and optical physics. In this paper we develop an efficient, systolic, re-configurable architecture for a particular type of FRFT called MA-CDFRFT (Multi Angle Centered Discrete FRFT). The benefit of this particular type of FRFT is that it computes all the signal components within equally spaced angles. Systolic architecture is used for this computation as it has certain advantages over the other forms like simplicity, regularity, concurrency and computation intensive The resultant product so developed should meet the challenges of today’s market like marketable and cheap along with meeting customer demands. This calls for the architecture to be re-configurable. Re-configurable computer consist of a standard processor and an array of re-configurable hardware. The main processor would control the behavior of the re-configurable hardware. The re-configurable hardware would then be tailored to perform a specific task, such as image processing or pattern matching applications, as if it was built to perform this task exclusively.
Keywords: MA-CDFRFT, Systolic Array, Up/down array, Re-configurable PE
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