Modeling and Simulation of Microcode-based Built-In Self Test for Multi-Operation Memory Test Algorithms
As embedded memory area on-chip is increasing and memory density is growing, newer test algorithms like March SS are defined to detect newly developing faults. These new March algorithms contain multiple operations per March element. This paper presents a microcoded BIST architecture which can implement these new March tests having number of operations per element according to the growing needs of embedded memory testing. This is shown by implementing March SS Test and testing for new faults including Write Disturb Fault (WDF), Transition Coupling Fault (Cft), Deceptive Read Disturb Coupling Fault (Cfdrd), which established tests like March C- are not capable of detecting. Verilog HDL code of this architecture is written and synthesized using Xilinx ISE 8.2i. Verification of the architecture is done by testing Mentor's ModelSim.
Keywords: Defect-Per Million (DPM;, Built-In Self Test (BIST); Memory Built-in Self Test (MBIST;, Microcoded MBIST; MUT (Memory Under Test.)
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