Static Noise Margin Analysis of SRAM Cell for High Speed Application
This paper presents the different types of analysis such as noise,
voltage, read margin and write margin of Static Random Access
Memory (SRAM) cell for high-speed application. The design is
based upon the 0.18 ?m CMOS process technology. Static Noise
Margin (SNM) is the most important parameter for memory
design. SNM, which affects both read and write margin, is
related to the threshold voltages of the NMOS and PMOS
devices of the SRAM cell that is why we have analyzed SNM
with the Read Margin, Write Margin and also the Threshold
voltage. For demand of the high-speed application of the SRAM
cell operation, supply voltage scaling is often used that is why
we have done Data Retention Voltage. We took different types
of curve by which straightforwardly we could analyses the size
of the transistor of the SRAM cell for high-speed application.
Keywords: Static Noise Margin, SRAM, VLSI, CMOS
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