Nurture IDR Segmentation and Multiple Instruction Queues in Superscalar Pipelining Processor
This paper proposes a model which improves the speed of the pipelining mechanism therefore increasing the speed of the processor. Superscalar operation is used to get maximum throughput from the processor using the pipelining concept. This proposal can be considered as the advancement of the super scalar property in pipelining which presently exists. We introduce a concept, using multiple instruction queues and a new unit called as Identifier unit. The Identifier unit is designed as having the ability of the identifying the type of the instruction which is being fetched and separating it based on its types thus creating separate segments of execution, which in turn increases the speed of the processor. Moreover we have implemented separate decoding and the executing unit for each type of the instruction segments.
Keywords: Pipelining, Superscalar property, Identifier unit and Multiple Instruction queue.
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ABOUT THE AUTHORS
J.Nandini Meeraa
pursuing bachelor’s degree in computer science and engineering third year at Narasu’s Sarathy Institute of Technology, Salem.member of CSI computer society. current research interest is on creating evolution in the speed of the processor.
N.Indhuja
pursuing bachelor’s degree in computer science and engineering third year at Narasu’s Sarathy Institute of Technology, Salem.member of CSI computer society. current research interest is on creating evolution in the speed of the processor.
S.Devi Abirami
pursuing bachelor’s degree in computer science and engineering third year at Narasu’s Sarathy Institute of Technology, Salem.member of CSI computer society. current research interest is on creating evolution in the speed of the processor.
K.Rathinakumar
Working as a lecturer at Narasu’s Sarathy Institute of Technology, Salem in the Department of Electronics and Communication Engineering. Approved by All India Council for Technical Education, New Delhi (AICTE) and is affiliated to Anna University of Technology, Coimbatore.; published paper in the international journal in the title of “ Efficient method for escalating the performance of programmable router for network on chip by lightweight circuit switched approach” in International Journal of Communication ,Computation and Innovation[IJCSI] of volume 1, issue 2(Jan-July 2011) of ISSN 2229-6808; published paper in the international journal in the title of “Multi Machine power system stabilizer design using particle swarm optimization technique” in International Journal of Communication ,Computation and Innovation[IJCSI] of volume 1, issue 2(Jan-July 2011) of ISSN 2229-6808; Presented a paper in National level conference on significant challenges of smart antennas in ADHOC networks at Idhaya Engineering College on 26th March 2011 conducted by department of CSE, ECE & IT in the title of National Conference on Advanced Computing and Communication Systems; Presented a paper in International level conference on channel noise cancellation using blind adaptive equalization at SSM college of engineering between September 21-23, 2011 conducted by Department of ECE in the title of International Conference on Computer Communication & Signal Processing (IC3SP)-2011;
J.Nandini Meeraa
pursuing bachelor’s degree in computer science and engineering third year at Narasu’s Sarathy Institute of Technology, Salem.member of CSI computer society. current research interest is on creating evolution in the speed of the processor.
N.Indhuja
pursuing bachelor’s degree in computer science and engineering third year at Narasu’s Sarathy Institute of Technology, Salem.member of CSI computer society. current research interest is on creating evolution in the speed of the processor.
S.Devi Abirami
pursuing bachelor’s degree in computer science and engineering third year at Narasu’s Sarathy Institute of Technology, Salem.member of CSI computer society. current research interest is on creating evolution in the speed of the processor.
K.Rathinakumar
Working as a lecturer at Narasu’s Sarathy Institute of Technology, Salem in the Department of Electronics and Communication Engineering. Approved by All India Council for Technical Education, New Delhi (AICTE) and is affiliated to Anna University of Technology, Coimbatore.; published paper in the international journal in the title of “ Efficient method for escalating the performance of programmable router for network on chip by lightweight circuit switched approach” in International Journal of Communication ,Computation and Innovation[IJCSI] of volume 1, issue 2(Jan-July 2011) of ISSN 2229-6808; published paper in the international journal in the title of “Multi Machine power system stabilizer design using particle swarm optimization technique” in International Journal of Communication ,Computation and Innovation[IJCSI] of volume 1, issue 2(Jan-July 2011) of ISSN 2229-6808; Presented a paper in National level conference on significant challenges of smart antennas in ADHOC networks at Idhaya Engineering College on 26th March 2011 conducted by department of CSE, ECE & IT in the title of National Conference on Advanced Computing and Communication Systems; Presented a paper in International level conference on channel noise cancellation using blind adaptive equalization at SSM college of engineering between September 21-23, 2011 conducted by Department of ECE in the title of International Conference on Computer Communication & Signal Processing (IC3SP)-2011;
